In various electronic devices it is desirable to switch between different clock signals. This is typically implemented by a clock switch having clock buffers and a multiplexer. The clock signals are buffered by the clock buffers. These clock buffers have a tristate mode. In the tristate mode the clock buffer output has a high impedance state (tristate buffer). In an example of the prior art a first tristate buffer receiving the first clock signal is switched into the high impedance mode and a second tristate buffer receiving the second clock signal is switched ON. This provides the buffered second clock signal at the output. The outputs of both buffers are coupled to a multiplexer. The multiplexer switches to output the required clock signal. The main problem with clock signal switching are glitches in the output signal that can occur if the multiplexer or buffer switching coincides with edges of a clock signal.
Glitches can be avoided by switching OFF the clock signals at a predefined moments synchronous with their edges. FIG. 1 illustrates such a switching procedure. A first clock signal CLK0 and a second clock signal CLK1 are supplied to a multiplexer. The multiplexer is controlled by a multiplexer control signal SEL_MUX. An asynchronous select signal ASYN_SEL indicates with a transition from low to high when the output of the multiplexer should be switched from outputting first clock signal CLK0 to outputting second clock signal CLK1. This system does not switch from first clock signal CLK0 to second clock signal CLK1 immediately. A synchronization step is first performed. The synchronized select signal SEL_SYNC is synchronized to first clock signal CLK1. Thereafter, multiplexer control signal SEL_MUX is switched from low to high in order to switch first clock signal CLK1 to the output of the multiplexer with a falling edge of first clock signal CLK1 with a rising edge of the asynchronous select signal ASYN_SEL. First clock signal CLK0 is initially locked in its current state (either 0 or 1). In the present example this is state 0. Therefore, the output signal CLKOUT remains at a logical 0 until the output of the multiplexer is switched in response to multiplexer control signal SEL_MUX. Glitches can still occur when a conventional clock switch is turned ON, i.e. when the switch is connected to the supply voltage. Clock switches according to the prior art therefore need a well defined RESET pulse to enter a valid initial state after powering up the electronic device. However, such an asynchronous RESET performed with a prior art clock switch fails to prevent all clock switching glitches.